We mainly support DDR3, DDR4 for customers who also doing SSD business, to brand customers or computer factories, we also has LPDDR which now only support China Inland major mobile phone and IPAD customers and some smart watch customers. With its high performance and lower consumption, its good for small size smart devices.
Dram/LPDDR Technical Parameter:
PRODUCT CATEGORYSPECIFICATION /
MAX DATA RATEDENSITYPACKAGEOPERATING
TEMPERATURE
DRAMDRAM D32Gb / 4GbFBGA 96 Ball25鈩儈85鈩?/p>
DRAM D44Gb / 8GbFBGA 96 Ball
DRAM ModuleU-DIMM4GB / 8GB / 16GB/32GB/0 鈩冿綖 85 鈩?/p>
SO-DIMM
R-DIMM8GB/16GB/32GB/0 鈩冿綖 85 鈩?/p>
LPDDRLP DDR42GB / 3GB / 4GB / 6GB / 8GB200Ball0 鈩冿綖 70 鈩?/p>
Specifications:
Product Model No.SpecificationDensityDimensionPackage
DRAM U-DIMM
/SO-DIMM8GB X8/X16
1.2V*2666/2933/3200Mbps8GB7.5 x 13.3mm
(W x L)78Ball/96Ball
DRAM U-DIMM
/SOD-IMM16GB X8/X16
1.2V*2666/2933/3200Mbps16GB10.3 x 11mm
(W x L)78Ball/96Ball
DRAM U-DIMM
/SO-DIMM32GB X8/X16
1.2V*2666/2933/3200Mbps32GB10.3 x 11mm
(W x L)78Ball/96Ball
Available module:
Part Number 1)DensityOrganizationComponent CompositionNumber of
RankHeight
4GB UDIMM4GB512Mx64512Mx16 * 4131.25 mm
8GB UDIMM8GB1Gx641Gx8 * 8131.25 mm
16GB UDIMM16GB2Gx641Gx8 * 16231.25 mm
4GB SODIMM4GB512Mx64512Mx16 * 4130 mm
8GB SODIMM8GB1Gx641Gx8 * 8130 mm
16GB SODIMM16GB2Gx641Gx8 * 16230 mm
NOTE:
1) (2133Mbps 15-15-15) / (2400Mbps 17-17-17) / (2666Mbps 19-19-19) / (3200Mbps 22-22-22) / (3200 Mbps 16-18-18) - DDR4-(3200Mbps 16-18-18) is backward compatible to lower frequency.
KEY FEATURES
SpeedDDR4-2133DDR4-2400DDR4-2666DDR4-3200DDR4-3200DDR4-3200Unit
15-15-1517-17-1719-19-1922-22-2219-19-1916-18-18
tCK(min)0.9380.8330.750.6250.6250.625ns
CAS Latency151719221916nCK
tRCD(min)14.0614.1614.2513.7511.87511.25ns
tRP(min)14.0614.1614.2513.7511.87511.25ns
tRAS(min)33323232.530.022.5ns
tRC(min)47.0646.1646.2546.2541.87533.75ns
鈼廕EDEC standard 1.2V 卤 0.06V Power Supply
鈼廣DDQ = 1.2V 卤 0.06 V
鈼?067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin 1333MHz fCK for 2666Mb/sec/pin,1600MHz fCK for 3200Mb/sec/pin
鈼?6 Banks (4 Bank G roups)
鈼廝rogrammable CAS Latency: 10 ,11,12,13,14,15,16,17,18,19,20,21, 22
鈼廝rogrammable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock
鈼廝rogrammable CAS Write Latency (CWL) = 11,14 (DDR4-2133), 12,16 (DDR4-2400) and 14,18 (DDR4- 2666) 鈥?Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
鈼廈i-directional Differential Data Strobe
鈼廜n Die Termination using ODT pin
鈼廇verage Refresh Period 7.8us at lower then TCASE 85飩癈, 3.9us at 85飩癈 < TCASE 飩?95飩癈
鈼廇synchronous Reset
FUNCTION BLOCK DIAGRAM for:
4GB,512M x 64Module ( Populated as 1rank of x16DDR4 SDRAMs )
NOTE :
1)聽 Unless otherwise noted, resistor values are 150惟聽 5 %.
2)聽 ZQ resistors are 2400惟 1%. For all other resistor values refer to the appropriate wiring diagram.
8GB,1Gx64Module (Populated as 1rank of x 8DDR4 SDRAMs)DDR wholesale
website:http://www.viccotech.com/ddr/